ISE 10.1 arrived at a time when FPGAs were becoming more complex, moving from simple glue logic to high-performance system-on-chip (SoC) platforms. This version brought several notable improvements:
To run ISE 10.1 on modern Ubuntu or CentOS: xilinx ise 10.1
ISE 10.1's synthesizer (XST) has a low default limit for loop unrolling. If your VHDL/Verilog code contains large for-generate loops, you will hit "XST: 1391 - Loop count limit exceeded." You must manually increase the "Loop Count Limit" in Synthesis Properties to 2000 or higher. ISE 10
Synthesis translates the HDL code into a gate-level netlist optimized for the target Xilinx device. xilinx ise 10.1
If you are reviving an old project, watch out for these issues:
ISE 10.1 refined the SmartCompile feature, which included: